Insights

Chiplet floorplanning: How to partition multi-die systems

The monolithic wall hits reality

Dr. Manish Bali, Sr. Director, Semiconductor vertical

Chiplet floorplanning is the process of partitioning a system across multiple dies and placing them on an interposer or substrate, optimizing cost, performance, power, and thermal behavior simultaneously. Unlike traditional single-die floorplanning, it requires full-system modeling, because every partition decision couples across thermal, power, and manufacturing domains. Get the die split wrong and no downstream optimization recovers it.

At the reticle limit of 858 mm², monolithic chip design stops.

You can't just grow die size anymore. Physics won't allow it. The semiconductor industry faces a fundamental scaling wall, and chiplets are the only path forward. But here's what most teams miss: chiplet floorplanning isn't traditional physical design extended across multiple dies. It's a completely different optimization problem.

In chiplet systems, every decision simultaneously ripples across thermal domains, power delivery networks, and manufacturing constraints . Get partitioning wrong, and you've locked in catastrophic failures. No downstream optimization recovers from bad die splits.

This is why most chiplet projects struggle. Teams treat it like traditional floorplanning with extra complexity, when they should be rethinking the entire optimization landscape.

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Why traditional floorplanning breaks

Traditional EDA flows assume a single die with known thermal characteristics, power, and signals on the same side. These assumptions collapse with chiplets.

Your interposer isn't passive routing. It's active silicon with electrical characteristics that matter. Power delivery spans multiple dies and the package. You can't analyze IR drop on one chiplet independently because shared power rails couple everything.

Thermal analysis transforms completely. One chiplet's power state changes the thermal environment for all neighbors. Adjacency effects dominate local hotspots. You must model the full system, not individual dies.

Verification explodes in complexity. You're verifying system-level interactions across heterogeneous dies from potentially different vendors, manufactured on different nodes, with different power domains. Cross-domain electrical, thermal, and mechanical coupling becomes mandatory analysis, not optional.

The result: traditional floorplanning tools don't work. They weren't built for this.

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The core partitioning challenge

Function-to-die assignment is the critical first decision. How you split compute, memory, I/O, and accelerators determines everything downstream.

Research demonstrates that intelligent partitioning, accounting for physical realizability, significantly reduces total system cost. Naive approaches that ignore implementation constraints fail spectacularly.

You must simultaneously optimize:

• Manufacturing cost (die size, packaging complexity, yield)
• Performance (inter-chiplet latency, bandwidth)
• Power delivery (voltage stability across dies)
• Thermal management (heat coupling between chiplets)
• Physical realizability (can you actually route it?)

No single objective wins. Every partition choice trades off multiple competing factors.

Here's the complication: Optimizing for cost by using mature nodes for memory sounds smart. Lower wafer costs. But level shifters at die boundaries add area, latency, and power. Was it worth it? That depends entirely on your application, volume, and power envelope.

This is why chiplet partitioning demands deep system understanding, not just physical design expertise.

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UCIe: The interface standard that changes everything

UCIe defines how chiplets communicate. Physical layer specs, die-to-die protocols, power management, everything.

Before UCIe, every company used proprietary interfaces. Mixing chiplets across vendors was impossible. Reusing IP blocks meant redesigning interfaces each time.

UCIe standardization enables modular approaches, reducing NRE through IP reuse. But standardization relocates complexity, not eliminates it.

Physical designers must now satisfy:

• Defined bump pitch requirements (25μm down to sub-1μm for 3D bonding)
• Standardized power and ground distribution
• Protocol latency and bandwidth constraints
• Reach limitations directly impacting floorplan feasibility

Advanced UCIe features includemanagement fabric for telemetry, security traffic padding, and dynamic rerouting around failures. These aren't nice-to-haves. They impact physical design from day one. Test access, power sequencing, and thermal monitoring can't be bolted on at the end. They must be architected into your floorplan upfront.

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Key implications for floorplanning:

CoWoS enables the highest-density integration with proven thermal management, but interposer routing constrains die placement. EMIB provides cost-effective 2.5D with moderate routing capacity. Organic substrate suits cost-sensitive applications but limits bandwidth. Hybrid bonding and direct bonding offer revolutionary density but introduce extreme thermal coupling requiring sophisticated modeling.

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Multi-die floorplanning: The methodology shift

Chiplet placement on the interposer or substrate determines system-level performance. Unlike traditional floorplanning, where blocks move within die boundaries, multi-die optimization repositions entire dies relative to each other and package resources.

Network topology decisions: Communication patterns among chiplets dictate placement. Different topologies optimize for throughput, minimize communication paths, or provide redundant routing. Network-on-Chip design must integrate floorplan information early to enable timing and power optimization before physical implementation.

Thermal management integration: Floorplan and power convergence matter from RTL through final layout. Early-stage power and thermal maps coordinate with package assembly and cooling design. Transient thermal-power modeling and temperature-sensitive parameter adjustments require upfront definition. Voltage and frequency throttling decisions depend on sensor placement and element proximity. These cannot be added at signoff.

Interposer routing constraints: Die placement must account for redistribution layer routing capacity. Bump assignment for macro-bumps and TSVs significantly impacts wirelength. Long interconnects degrade performance and increase power. Placement optimization minimizes critical path lengths between communicating dies while respecting congestion and reach constraints.

Heterogeneous integration advantages: Different dies use different process nodes optimized for function. Compute on leading-edge 3nm for performance, memory on mature nodes for cost efficiency, analog/RF on specialized processes. Research demonstrates that heterogeneous integration reduces costs compared to homogeneous approaches, but requires careful voltage-domain planning and level-shifter integration at die boundaries.

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Power delivery complexity across dies

System PDN spans multiple dies, packages, and PCBs. Each chiplet has local requirements, but system-level coordination ensures stable voltage under dynamic load conditions.

Current must flow from the package, through the interposer to the chiplet. Resistance and inductance accumulate. IR drop analysis requires full-system modeling. Analyzing chiplets in isolation misses critical interactions. Package-level voltage regulators must coordinate with on-die regulation schemes.

Power gating introduces sequencing complexity. When chiplets gate internal domains, shared power rails couple effects across the system. Interface power management protocols (UCIe L1/L2 states) require physical design support for rapid transitions without glitching adjacent circuitry.

Thermal-power coupling spans chiplets. One die's power state affects the thermal environment of its neighbors.Early floorplan decisions about spacing and orientation directly impact coupled thermal-power behavior. You can't optimize power independently of thermal.

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Tools and optimization approaches

Recent EDA advances address multi-die complexity. Major vendors provide analysis-driven exploration, partitioning, and floorplanning for full-stack designs with automated die-to-die routing and multi-die signoff. Advanced platforms offer unified interfaces for chiplet, interposer, and package design planning with multiphysics analysis.

System-Technology Co-Optimization (STCO) extends design-technology co-optimization to the system level, incorporating 2.5D/3D packaging, die-to-die interconnects, architecture, and software. STCO determines how complex systems should be partitioned and assembled to achieve optimal PPA, cost, and reliability. As designs scale toward wafer-level modular systems, STCO becomes mandatory.

Machine learning models now guide floorplan exploration, predict congestion before implementation. They also optimize placement under thermal constraints and generate cost-aware partitions balancing manufacturing and packaging expense.

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When chiplets make economic sense

Chiplets aren't universally cheaper. Advanced packaging adds cost. Multiple dies mean multiple tapeouts. Design complexity increases NRE. So when does the math work?

High-volume products at reticle limits: Breaking monolithic dies into chiplets dramatically improves yield. Yield scales exponentially with die size. Smaller dies have exponentially better wafer yield. For high volumes, this improvement justifies packaging costs.

Heterogeneous integration requirements: When different functions need different nodes (leading-edge logic, mature memory), chiplets enable mixing impossible monolithically. Process node savings often outweigh packaging costs.

Design reuse across products: First product absorbs chiplet NRE. Second- and third-product reuse existing chiplets, enabling faster time-to-market and lower NRE. Economics improve dramatically with amortization.

Performance beyond single-die capability: When bandwidth, compute density, or memory requirements exceed the largest manufacturable die, chiplets provide the only path. AI accelerators with HBM exemplify this. Monolithic approaches can't scale these applications.

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Best practices for floorplanning teams

1. Architecture before layout: Define communication patterns, bandwidth requirements, latency budgets, and power envelopes before floorplanning. Partitioning driven by physical constraints without architectural grounding produces infeasible solutions.

2. Thermal modeling from day one: Thermal issues aren't local. One chiplet's heat affects all neighbors through the package substrate. Full multiphysics modeling is required, not back-of-envelope estimates. Make thermal decisions during floorplanning, not after tapeout.

3. Physical reach validation: Die-to-die transceivers have limited reach. UCIe specs define maximum bump pitch and length. Don't assume connections will route. Generate actual RDL solutions during floorplan exploration. Violations found post-implementation require respins.

4. Package co-optimization: Die and package design are coupled problems. Weekly coordination between silicon and package teams prevents late-stage failures. Share power maps, thermal profiles, and mechanical constraints bidirectionally.

5. Test and debug architecture: Multi-die bring-up requires early planning. UCIe management fabric, scan access across die boundaries, and debug visibility need floorplan integration. Ad-hoc solutions added late fail.

6. Standards with customization: UCIe provides a foundation. Use it where applicable. Custom protocols may optimize specific use cases. Balance interoperability against optimization requirements. Document deviations clearly.

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The inflection point is now

By the end of 2026, chiplet adoption will accelerate across all market segments. TSMC's CoWoS capacity is heavily subscribed. Intel's EMIB and Foveros ramp volumes. AMD's chiplet-first strategy dominates the datacenter.

Hyperscalers design custom chiplet-based AI accelerators with each generation pushing boundaries. Automotive adopts chiplets for domain controllers. Mobile processors explore heterogeneous integration. Edge devices use chiplets to achieve a cost-performance balance.

The transition is happening across every segment.

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The methodology imperative

Chiplet floorplanning requires:

• System-level thinking across multiple dies and technologies
• Deep understanding of packaging, thermal, and power delivery
• New tools built for multi-die complexity
• Cross-functional collaboration between silicon, package, and test teams

Teams that master these disciplines define the next decade of semiconductor innovation.

Those that don't will struggle to remain competitive.

Chiplet complexity isn't optional anymore. It's mandatory for advanced node design.

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Get the die split right the first time.

Bad partitioning locks in failures no downstream optimization can recover. UST's pre-silicon engineering teams bring system-level thinking across die, package, thermal, and power so your chiplet architecture is feasible before tapeout.

Explore UST pre-silicon engineering

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Resources

Silicon Engineering & Semiconductor Design Services | UST

Physical design in 2025: Advanced node transitions and new methodologies

Timing closure at 3 nm: strategies, ECO precision & AI breakthroughs

Clock tree synthesis optimization at advanced nodes: Mastering the complexity of 3nm and beyond