Insights

Physical design in 2025: Advanced node transitions and new methodologies


Swasti Pujari, Practice Head - VLSI Backend, UST

Here’s something that keeps every chip designer awake at night: the methodologies that worked perfectly at 7 nm are breaking down at 2 nm.

Swasti Pujari, Practice Head - VLSI Backend, UST

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The 2nm reality check

TSMC’s 2 nm process promises 10-15% higher performance at the same power, or 25-30% lower power at the same performance, compared to its 3 nm process. Transistor density improves by around 15-20%. These numbers are real and come directly from TSMC’s official communications.

But here’s what most engineers miss: achieving these gains requires completely new physical design methodologies. The tricks that worked at 5 nm or 7 nm no longer apply.

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Gate-All-Around transistors redefine everything

Gate-All-Around (GAA) nanosheet transistors are forcing physical designers to rethink placement and routing from the ground up. This is the first major architectural shift since planar transistors gave way to FinFETs.

Samsung’s Multi-Bridge Channel Field Effect Transistor (MBCFET) structure is an example of GAA in production. It delivers strong gains in power and area efficiency compared to FinFETs, but its design ecosystem is still maturing. IP qualifications and verification take significantly longer and cost more than previous generations.

Manufacturing GAA devices is also far more complex. Stacking nanosheets and wrapping the gate material with atomic precision requires entirely new materials and etching methods. For physical designers, this translates into new rules for spacing, parasitic modeling, and layout density. Every placement and routing decision must now consider these nanosheet-specific effects.

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The rise of Backside Power Delivery

Backside Power Delivery Networks (BSPDN) are changing how we think about power integrity and routing. This new architecture moves power routing to the backside of the wafer, separating it from signal routing.

Intel’s PowerVia technology is the most prominent implementation. It routes power through deep vertical connections called through-silicon vias, reducing resistance and improving power efficiency. While this approach shortens power paths and improves voltage stability, it also requires new strategies for floor planning, power grid design, and thermal management.

However, it’s important to note that TSMC’s 2 nm process will not yet use backside power delivery. The company plans to introduce it in its next-generation A16 process. So, while the concept is real and transformative, it is still at an early adoption stage across the industry.

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Design-technology co-optimization is now essential

Design-Technology Co-Optimization (DTCO) is no longer optional. As we enter the Ångström era, the advantages of simple transistor scaling are fading. Achieving performance, power, and area (PPA) targets now requires a deep collaboration between design and process technology teams.

DTCO includes optimizing standard-cell architecture, power-rail configuration, interconnect schemes, and even micro-TSV placement. Physical designers can no longer treat design and technology as separate domains. Every decision affects both sides.

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AI is powering the new design flow

AI and machine learning are now integral to modern electronic design automation (EDA). At events like CadenceLIVE India 2025, the focus has shifted toward AI-assisted physical design.

Cadence and Synopsys are embedding machine learning into tools for placement optimization, routing congestion prediction, and timing closure. These AI features don’t replace engineers, but they enable engineers to explore vast design spaces much faster. Instead of manually tuning hundreds of parameters, designers can rely on AI to identify optimal configurations that balance timing, area, and power.

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Variability and yield at 2-nm

At 2 nm, process variability dominates. Random dopant fluctuations, line-edge roughness, and lithography imperfections can significantly alter transistor behavior.

Physical design teams now rely on statistical timing analysis, variation-aware optimization, and multi-corner multi-mode (MCMM) simulations. These tools model thousands of operating conditions to ensure designs meet timing and power goals across all possible variations.

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The complexity of 3D integration

Modern physical design doesn’t stop at a single die. Designers are now working with 3D stacking, through-silicon vias (TSVs), and heterogeneous integration.

Optimizing in three dimensions adds new challenges for thermal management, power delivery, and signal integrity. The physical design flow must now coordinate X, Y, and Z placement decisions, as well as interactions between dies built using different process technologies.

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What’s next for physical designers

The implementation of GAA transistors and backside power delivery is already showing measurable benefits. Early adopters report improvements in power integrity and routing efficiency, with reduced IR drops and better timing closure.

However, these results depend heavily on AI-enhanced tools and tight DTCO practices. The complexity is unprecedented, but the payoffs are equally large.

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Final takeaway

Physical design in 2025 is not about incremental upgrades. It’s a full-scale transformation.

To stay relevant, every physical designer must master:

Those who adapt will define the next decade of semiconductor design. Those who don’t will be left behind.

The future of physical design belongs to the engineers who embrace change today.

Ready to master the future of chip design?

The transition to 2 nm demands more than incremental tweaks; it requires a complete rethink of physical design. From Gate-All-Around transistors to AI-powered EDA, the rules have changed.

Dive deeper into the methodologies shaping tomorrow’s silicon:

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