Insights
RISC-V: The underdog chip poised to reshape the tech landscape
Unveiling the potential: RISC-V's versatility in revolutionizing the computer industry
Manish Bali, Sr. Director & Head, Pre-Silicon & Embedded
From discovery to delivery and beyond, UST aids diverse organizations across domains through successful RISC-V open ISA implementations. We can help you discover if your applications and business can benefit from the RISC-V open ISA architecture and its expanding innovative ecosystem.
Manish Bali, Sr. Director & Head, Pre-Silicon & Embedded
OEMs and silicon vendors are invariably seeking new ways to improve processing performance, flexibility, efficiency, and CPU designs that can handle the performance and power requirements of newer workloads from Artificial Intelligence (AI), machine learning, deep learning, Internet of Things (IoT), virtual/augmented reality, cloud servers, network edge, and other modern resource-intensive applications.
As a promising answer to these challenges, the open RISC-V ISA multicore processor has gained significant attention in recent years. It allows developers to design custom CPUs based on an application's performance, power consumption, and affordability needs.
The ability to fine-tune performance and power at the application level captivates chip developers, OEMs, and manufacturers. It resonates across businesses requiring high-performing computers to run their modern applications effectively at peak performance. This is accomplished through the modular design of RISC-V.
It wasn't long ago when the notion of combining a modular approach with open-source ISAs was inconceivable to many. RISC-V represents a new era of processor design innovation with great potential to reimagine the future of the computing industry.
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What is RISC-V?
Every computer processor has a set of instructions that specify how the processor should be coded and executed, known as an instruction set architecture (ISA). Pronounced risk five, the RISC-V Core for microprocessors and microcontrollers is a modular open standard ISA.
More specifically, RISC-V comprises a small general base ISA and various ISA extensions compared to Complex Instruction Set Computing (CISC), which uses a large set of multiple instructions. CISC processors that use proprietary ISAs like Intel x86 and ARM typically require more cycle times to execute instructions (many times due to complex instruction getting multiple micro-coded instructions), while RISC-V processors can execute instructions in a single cycle.
The smaller energy-efficient modular design of RISC-V with optional ISA extensions simplifies the instructions given to the processor to execute tasks. It allows developers to create a diverse array of custom processors for various markets quickly and efficiently. The modularity of RISC-V gives developers the flexibility to choose from available features instead of using the complete feature set, accelerating development time and helping companies get to market faster with their designs.
As an open-source ISA, anyone can implement RISC-V on microprocessors or microcontrollers without paying licensing or royalty fees, contrary to proprietary ISAs found in CISC processors.
The RISC-V ISA accelerates development cycles while enabling targeted performance and energy efficiency, making the open-source processor better suited for resource-intensive applications that often require real-time decision-making and actions.
RISC-V aims to reduce the reliance on proprietary ISAs and remove the complexity in designing processor cores.
The RISC-V concept began in 2010 as a UC Berkeley's Parallel Computing Laboratory research project. Today, RISC-V is in its fifth generation, and RISC International is a global nonprofit organization that owns the RISC-V ISA intellectual property. The RISC-V Foundation is its membership organization, comprising 3,950 members across 70 countries, including academic institutions, nonprofits, government agencies, individuals, and influencers in the processor industry, including Alibaba Group, Google, Intel, Nvidia, Qualcomm, SiFive, and the open-source consortium Linux Foundation. These members are responsible for promoting, advancing, and standardizing RISC-V and maintaining the RISC-V specifications and documentation.
Today, RISC-V adoptions are growing in sync with the rising demand for efficient, customized CPUs that support the newer workloads of this era's advanced applications.
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The advantages of RISC-V
RISC-V has many advantages for developers and manufacturers compared to proprietary ISAs like x86 and ARM. The most notable include:
- Openness: RISC-V's primary differentiator is its open-source nature. Unlike expensive propriety ISAs used in CISC processors, the RISC-V ISA is open to anyone and free of licensing and royalty fees. The RISC-V community-driven open ISA drives collaboration and innovation across industry. The open ISA instills transparency and trust with freely available ISA specifications and extensions that anyone can scrutinize.
- Versatility: Due to its modular design, RISC-V can cover diverse domains across various applications and functions, from data centers to embedded systems, machine learning modeling, high-performance computing environments, and IoT devices. RISC-V can handle more domain-specific requirements, adjust resources to accommodate changes in demand, and quickly scale, making it one of the most adaptable processors in the industry.
- Extensibility: Customizing the ISA to meet specific application needs is a crucial differentiator for the RISC-V architecture. RISC-V uniquely blends a modular design with the ability to add custom instructions to an open-source ISA. RISC-V can customize CPUs to their core, allowing developers to build application-specific processors that can improve performance and energy at the application level.
- Simplicity: RISC-V prioritizes simplicity by using a small set of ISA instructions with extensions that execute one instruction per clock cycle, unlike CISC processors that use a larger set of complex instructions that may require multiple clock cycles. With fewer and simpler instructions, RISC-V enables easier chip design making, reduces complexity, accelerates development cycles, and simplifies hardware and software optimization.
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RISC-V adoption challenges
Despite its progress, ingenuity, and growing popularity, there are some challenges and hurdles to consider when implementing RISC-V architectures, most notably:
- Compatibility issues: RISC-V is incompatible with other ISA implementations or software built for other ISAs. A RISC-V implementation can require code recompiling.
- Maturing ecosystem: As a late bloomer in the processor industry, RISC-V still lags in market adoption compared to traditional ISAs. However, RISC-V implementations are increasing, driven by AI, machine learning, and other resource-demanding applications. This momentum is helping the RISC-V community level the playing field.
- Technical complexities: The RISC-V software community is developing rapidly, but it still can't compare to traditional ISAs regarding software availability, compilers, and tools. Migrating existing software to RISC-V can be tricky and may require technical guidance.
- RISC-V verification: No single company or team designs and verifies RISC-V cores. The RISC-V ISA specification and its extensions contain many choices and custom instructions. Therefore, most RISC-V implementations require an independent verification solution to confirm that designs are compatible and comply with the RISC-V ISA specification. Instruction Set Simulator (ISS), which is a golden reference for verifying any hardware design, must be modified to be able to generate the “golden result” accurately.
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The massive momentum of RISC-V
RISC-V technology's prospects and potential growth are seemingly endless if the demand for tailored CPUs and newer workloads like AI and IoT continues, which is inevitable. Research firm Semico confirms this upward trend, indicating the number of chips that contain at least some RISC-V technology will grow 73.6% per year through 2027, driven by the rising demand for AI and machine learning applications.
Here are some major moves from last year that provide a glimpse into the future of RISC-V ISA awareness, pervasiveness, and nonstop momentum.
- In November 2023, Google announced plans to have Android on CPUs built on RISC-V, prompting developers to prepare for this move, which would put RISC-V in the hands of billions of users.
- Bosch, Infineon, Nordic, NXP, and Qualcomm financed a company to advance the global adoption of RISC-V.
- Google, Intel, NVIDIA, Qualcomm, Red Hat, and Samsung activated the RISE project, which was formed to accelerate software development for RISC-V architectures.
- Established architecture in automotive and AI accelerators.
- Ecosystem maturing rapidly for consumer and infrastructure markets.
Well on its way to widespread adoption, the RISC-V multicore processor is projected to be used inside 16 billion chips by 2030, far from its current 1 billion shipments. Those organizations adopting RISC-V today will seize the benefits for decades and flourish in the new world of open, custom CPU designs.
From discovery to delivery and beyond, UST aids diverse organizations across domains through successful RISC-V open ISA implementations. We can help you discover if your applications and business can benefit from the RISC-V open ISA architecture and its expanding innovative ecosystem.
DIVIDER