Insights

The real test of RISC V in automotive is execution

By Gilroy Mathew, Chief Operating Officer, UST

Originally featured in DIGITIMES Asia: “India does the heavy lifting: RISC-V moves into cars and factories.”

The semiconductor industry has rarely moved in straight lines. Architectural shifts that look inevitable on paper tend to stall, fragment, or accelerate in ways nobody predicted, and RISC-V is following that pattern with precision. The open instruction set architecture is genuinely gaining commercial traction. But the question being asked in boardrooms and design centers across the automotive supply chain is not whether RISC-V will matter. It is whether organizations have the execution discipline to make it work at automotive-grade levels on automotive timelines.

At UST, we are in the middle of multiple RISC-V programs, including joint SoC development with a Bengaluru-based partner targeting safety-critical automotive systems, factory automation, and real-time control workloads. What we have learned from that work is that RISC-V’s biggest challenge is not the instruction set. It is everything that surrounds it.

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The commercial case is real, and specific

The market numbers behind RISC-V are striking. According to Mordor Intelligence, the global RISC-V technology market was valued at approximately $1.35 billion in 2025 and is forecast to grow to $10.7 billion by 2031, at a compound annual growth rate of 41.21%. Automotive and transportation are among the fastest-growing application segments, tracking at a 57.6% CAGR through 2031, per the same analysis. Research from Grand View Market Insights places the broader RISC-V market at $2.30 billion in 2025, scaling toward $25.73 billion by 2034 at a 30.7% CAGR, with custom RISC-V architectures, the segment most relevant to automotive, growing at 33.6%.

Unit shipment data from The SHD Group paints an equally clear picture: automotive RISC-V SoC shipments are projected to grow from 55 million units in 2024 to approximately 139 million units in 2026, and nearly 490 million by 2030; a 49.5% CAGR that outpaces most other application categories.

These numbers reflect a real shift, not a speculative one. Semiconductor companies are experimenting seriously with RISC-V as an alternative to incumbent architectures in domain controllers, ADAS subsystems, industrial automation, and edge computing. The architecture’s appeal is genuine: it is open, modular, license-free, and critically for automotive purposes. It allows the customization and long-term cost control that OEMs and Tier-1 suppliers increasingly need as software-defined vehicles place new and unpredictable compute demands on the underlying silicon.

“RISC-V makes commercial sense where customers want differentiated, workload-specific silicon rather than general-purpose CPUs,” is how I put it in the DIGITIMES Asia interview. That framing is deliberate. The commercial case for RISC-V is not broad. It is specific. It is strongest in lower-volume, highly customized designs, particularly in automotive and industrial segments, rather than in consumer electronics or high-volume general-purpose processors where Arm and x86 have deep software ecosystems and proven tool chains that are extremely difficult to displace.

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ADAS: The highest-stakes near-term battleground

Advanced driver assistance systems represent both the most promising near-term market for RISC-V deployment and its most demanding test environment. ADAS now encompasses everything from adaptive cruise control and lane-keep assist to automatic emergency braking, surround-view processing, and the sensor fusion stacks that underpin Level 2+ and Level 3 autonomy. Each of these subsystems requires silicon that is not only high-performance but also certified, specifically, compliant with ISO 26262 at the Automotive Safety Integrity Level (ASIL) appropriate to the function's risk exposure.

ASIL-D, the highest level under ISO 26262, requires redundancy, real-time diagnostics, and fail-safe mechanisms built directly into hardware. As noted by Ansys, automotive ICs designed for safety-critical applications must also demonstrate reliable operation throughout the typical vehicle lifecycle of 10 to 15 years, a requirement that creates a fundamentally different design and validation problem than consumer or industrial electronics.

This is where RISC-V’s customization advantage begins to feel the pressure of automotive reality. An open instruction set means you own the architecture decisions, but it also means you own the verification workload. For established platforms like Arm Cortex-R, automotive-grade safety certification tools, IP libraries, and OS-level support are mature. For RISC-V, those assets are improving but they are not yet at parity.

The shift toward software-defined vehicles is intensifying these demands further. Modern vehicles increasingly centralize compute through domain controllers, single SoCs handling what were previously distributed ECUs across the vehicle. This consolidation sharply increases compute requirements and raises the stakes on any architectural decision made early in the design cycle. Mobileye’s EyeQ Ultra, for instance, incorporates 12 dual-threaded RISC-V CPU cores in a chip aimed at full-stack autonomy, a signal that RISC-V can play in high-performance ADAS, but also evidence that even the most capable adopters are doing so within a carefully bounded deployment context.

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The execution bottleneck is the real problem

What distinguishes genuinely experienced RISC-V practitioners from enthusiastic observers is a clear-eyed recognition of where the friction actually lives. The constraint on adoption is not architectural capability. It is execution.

RISC-V offers customization and long-term control but demands stronger execution discipline. That execution gap shows up across three interlocking dimensions.

Verification workloads are heavier. RISC-V designs require a greater upfront investment in verification than those of mature architectures with established IP libraries. This is not a permanent condition, it is a function of ecosystem maturity, but it is a present reality that directly affects design cycle length and cost. For automotive programs with fixed SOP dates and long qualification windows, every additional verification cycle carries schedule risk that is difficult to absorb.

Software readiness lags. Despite noticeable improvement over the past two years, RISC-V's operating system support and software tooling continue to trail those of incumbent platforms. Failure to align silicon design, firmware, and system software early in the development cycle does not just create delays in automotive contexts; it creates time-to-market risk that cascades across the entire vehicle program.

System integration is underestimated. RISC-V does not ship in isolation. It ships with an in-vehicle E/E architecture that includes specific real-time requirements, safety partitioning, inter-domain communication protocols, and thermal constraints. The work of integrating RISC-V cores into that environment, particularly alongside legacy MCUs and existing software stacks, is substantial and cannot be compressed by architecture choice alone.

“Execution issues translate quickly into time-to-market risk.” Automotive companies are under intense and intensifying competitive pressure. The race to compress development timelines, while simultaneously meeting functional safety certification requirements, leaves almost no margin for architectural experiments that stall during verification and integration.

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India’s expanding role: execution hub, not just back office

One of the most significant structural shifts accompanying RISC-V adoption is the growing depth of engineering work being sent to India. This is not about offshore cost arbitrage. It is about where high-complexity execution capability is being built and deployed.

UST’s India-based teams are deeply involved in SoC enablement, verification, firmware development, edge AI, and post-silicon support for global semiconductor, automotive, and manufacturing customers. The nature of this work has changed considerably. What was once primarily a back-office function, running regression tests, maintaining documentation, has become a substantive part of the design and enablement process. Architectural decisions may still originate elsewhere, but the technical depth of what is executed in India is growing.

“Once engineering R&D moves into India, the value chain moves up.” This is happening in real time. The skills shortage in semiconductor engineering globally, verification engineers with RISC-V experience, firmware architects who understand functional safety frameworks, post-silicon validation specialists, is one of the primary constraints on the pace of RISC-V adoption in automotive. India’s expanding talent base, combined with closer industry-academia collaboration and investment from global chip companies, is becoming a structural advantage in addressing that constraint.

UST is also pushing beyond design into the broader semiconductor lifecycle. A joint venture with Kaynes Semicon to establish an OSAT (Outsourced Semiconductor Assembly and Test) facility, combined with the importation of packaging and testing expertise from Malaysia and Taiwan to train local teams, reflects a deliberate strategy to build India into a broader execution hub, not a narrowly specialized design center.

At the technical frontier, UST’s teams are developing customer SoCs using the Posit numeric system on RISC-V architectures. Posit arithmetic, a tapered-precision alternative to traditional floating-point, improves numerical accuracy and computational efficiency in ways that are particularly relevant for AI inference, signal processing, and other compute-intensive ADAS workloads. This kind of workload-specific differentiation, enabled by RISC-V’s architectural openness, is precisely the domain where the architecture’s commercial value is most defensible.

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The path forward: Anchor customers and ecosystem discipline

Broader RISC-V adoption in automotive will not be driven primarily by government incentives, industry consortia, or architectural evangelism. It will be driven by commercial execution, specifically, by anchor customers committing to production deployments and pulling the broader ecosystem forward through volume.

RISC-V is not a replacement for Arm or x86 in mainstream automotive markets, and it is unlikely to become one in this decade. Semiconductor companies will continue to rely on established architectures where software maturity and predictable time-to-market remain decisive. The right frame is not displacement; it is complementarity. RISC-V is earning its place in a portfolio of architectural choices, particularly for domain-specific control functions, safety monitors, ADAS subsystem processors, and edge AI accelerators, where customization creates durable differentiation.

Infineon, notably, has publicly targeted 2028 for its first RISC-V automotive chip rollout, a timeline that reflects both the opportunity and the realistic pace of automotive-grade validation. That kind of anchor commitment, from a company with deep automotive ecosystem relationships and functional safety expertise, is exactly the signal the broader supply chain needs.

For UST, the opportunity is unambiguous. The combination of chip-to-cloud engineering capability, safety-critical execution experience, and India’s expanding semiconductor workforce positions us precisely at the intersection where RISC-V’s architectural promise meets automotive’s execution demands.

The architecture is ready enough. The question is whether the organizations deploying it have built the verification depth, software readiness, and system integration discipline that the automotive industry requires. That is a question of execution. And execution is what we do.

Turn RISC-V promise into automotive-grade reality. See how disciplined execution across silicon, software, and safety can de-risk timelines and unlock real differentiation. Talk to UST about building RISC-V systems that ship.

Resources

https://www.ust.com/en/engineering

https://www.ust.com/en/automotive-solutions

https://www.ust.com/en/ust-idec