Insights

Backside power delivery network: The physical design revolution at 2nm

The paradigm shift in power delivery

Dr. Manish Bali, Sr. Director, Semiconductor vertical

In the race to angstrom-class nodes, one technology stands poised to redefine physical design: Backside Power Delivery Network (BSPDN). After decades of routing both power and signals on the front side, foundries are literally flipping the wafer. TSMC's A16 with Super Power Rail, Intel's PowerVia at 18A, and Samsung's 2GAP roadmap all converge on a singular truth: backside power is no longer optional. It's the unlock for continued scaling.

At 2nm and beyond, power delivery isn't just about IR drop mitigation. It's about reclaiming routing resources, enabling higher utilization, and breaking through the congestion ceiling that has constrained advanced nodes. BSPDN represents the most significant interconnect architecture shift since copper replaced aluminum in 1997. The question isn't whether BSPDN will dominate.

The question is: are physical design teams prepared to architect for it?

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What is BSPDN and why is it transformative?

Backside Power Delivery Network (BSPDN) dedicates the wafer’s backside exclusively to power distribution, decoupling power from signal. Traditional designs route VDD and VSS through the same metal stack as signals, consuming about 20% of frontside routing resources — a bottleneck that compounds at 3nm and below into congestion, IR drop across 15+ metal layers, and power-signal noise coupling.

By moving power to the backside, BSPDN reclaims those resources. The gains are architectural, not incremental:

1. Performance: Intel reports PowerVia delivers a 6% frequency improvement and 30% power-loss reduction. TSMC’s A16 Super Power Rail targets 8–10% performance over N2P.
2. Area: Samsung reports 17% die-size reduction versus frontside power at 2nm. Intel’s Blue Sky Creek test chip demonstrated over 90% cell utilization.
3. Signal integrity: Isolating power reduces noise coupling, improves voltage stability, and enables cleaner signal routing with fewer conflicts.

This is the most significant interconnect architecture shift since copper replaced aluminum in 1997.

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What are the three paths to backside power?

The industry has converged on BSPDN but diverged on implementation. Three architectural approaches define the landscape, each trading manufacturing complexity against scaling benefit.

Traditional backside contact (simplest): Routes power through deep vias from rails around transistors up to M1, thendown through top contact. Lower manufacturing complexity, moderate scaling benefits, reduced initial risk.

PowerVia with nanoTSVs (Intel 18A): Connects backside power directly to buried power rails through nano-scale through-silicon vias. Intel proved this approach with Blue Sky Creek, achieving superior scaling while managing manufacturing feasibility. The 18A node combines this with RibbonFET GAA transistors for up to 36% power gains.

Direct connect to source/drain (TSMC A16): Links backside microvias directly to each transistor's source and drain. The highest scaling potential but requires precise photolithography alignment on thinned, bonded wafers. TSMC's Super Power Rail technology minimizes resistance by shortening the power delivery paths to the transistor level.

Timeline: Intel ships first with PowerVia at 18A in mid-2025. TSMC follows with A16 in H2 2026. Samsung plans BSPDN for its 2GAP node in 2027.

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How does BSPDN change physical design?

BSPDN fundamentally alters physical design methodology. Engineers move from managing power-signal trade-offs to optimizing two independent networks. Six things change.

Floorplanning liberation: Power grids no longer constrain M1 resources. Blocks achieve higher utilization rates. Pin placement gains flexibility. Power routing channels between blocks become optional, not mandatory.

Standard cell evolution: Cell libraries shed power rail tracks, enabling heights below 6T. Buried power rails replace BEOL power structures. Cell-to-cell spacing requirements shrink. Pin locations and access patterns shift.

Placement density: Utilization targets climb from 75-80% to 90%+ as power blockages disappear. Placement flexibility increases for timing optimization. Congestion hotspots shift from power-dominated regions to pure signal routing challenges.

Routing transformation: M1 and M2 become fully available for signal routing. Congestion analysis changes fundamentally; power no longer competes for resources. Wiring length reduces by over 9% according to Intel data.

Timing closure redefined: Reduced IR drop means more stable voltage delivery and predictable timing. Lower power noise improves signal integrity. But nTSV parasitics introduce new modeling requirements, and substrate coupling effects demand updated analysis.

Power integrity: IR drop analysis extends across front and backside networks. Dynamic voltage simulations must account for substrate coupling. Decap placement strategies optimize for BSPDN topology, not traditional frontside grids.

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What does BSPDN cost to manufacture?

BSPDN demands extreme manufacturing precision. Wafer thinning to under 500nm, processing nano-TSVs with 100nm diameters (versus 10μm for traditional TSVs), photolithography alignment on bonded wafers, and backside metallization after frontside completion, all introduce new process steps.

Intel 18A uses 14 frontside layers, four backside layers, and a redistribution layer, 18 total versus 15 for Intel 4. TSMC's approach requires aligning backside lithography to frontside features on thinned wafers, introducing distortion challenges.

The cost impact is real but justified. BSPDN adds process complexity yet improves scaling, delivering cost-per-transistor advantages. Early adopters target performance-critical products where benefits outweigh incremental costs: HPC processors, AI accelerators, and premium mobile chips.

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Is the ecosystem ready for BSPDN?

Technology means nothing without tools to implement it. BSPDN readiness varies across the ecosystem:

EDA tools: Major vendors support BSPDN flows, but maturity differs. Power integrity analysis tools require updates for backside modelling. Place-and-route engines optimize for new cell structures. Verification flows add complexity for cross-side connectivity checking.

Standard cell libraries: Foundries provide BSPDN-optimized libraries, but characterization data is still maturing. Multiple track heights accommodate different performance targets. Custom library development requires understanding new design rules.

IP availability: Third-party IP for BSPDN nodes is expanding but not yet comprehensive. IP migration from traditional architectures demands revalidation. Custom IP development requires specialized knowledge of backside power interfaces.

Design services: Partners with early BSPDN experience hold competitive advantage.

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Where does BSPDN deliver the most value?

Not every design demand backside power. Strategic deployment focuses on applications where benefits justify complexity:

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How should physical design teams prepare?

BSPDN adoption accelerates through 2026–2027 as A16, 18A, and 2GAP reach volume. Teams should act now across five fronts.

1. Foundry engagement: Understand PDK specifics for target nodes. Participate in early library characterization. Influence standard cell development based on design needs.

2. Methodology evolution: Update floorplanning guidelines for backside power. Revise power planning scripts and automation. Develop verification flows for front-to-backside connectivity.

3. Tool qualification: Validate EDA tool support for BSPDN modeling. Test power integrity analysis accuracy. Confirm timing analysis includes backside parasitics.

4. Team training: Build expertise in BSPDN design principles. Understand manufacturing constraints. Practice on test chips or early adopter designs.

5. IP strategy: Assess existing IP for BSPDN compatibility. Plan migration paths for critical blocks. Develop new IP optimized for backside power architecture.

The competitive imperative BSPDN adoption accelerates through 2026-2027 as A16, 18A, and 2GAP reach volume production. Companies mastering backside power design will ship products with superior PPA while competitors struggle with migration.

The transition isn't optional. All leading-edge foundries commit to BSPDN for angstrom-class nodes. The choice is lead or follow.

The era of backside power has arrived. The question is: will your designs be ready to leverage it?

UST’s pre-silicon engineering teams bring backside-aware floorplanning, power integrity, and signoff expertise to 2nm and angstrom-class designs — so your PPA advantage is built in from day one.

Explore UST pre-silicon engineering

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Frequently asked questions

Q: What is a backside power delivery network (BSPDN)?

A: BSPDN moves power distribution to the wafer’s backside, dedicating the frontside to signal routing. Decoupling power from signal eases congestion and improves performance at 2nm and below.

Q: Why does BSPDN matter at 2nm?

A: Power and signal competing for the same metal stack create congestion and IR drop. BSPDN frees roughly 20% of frontside routing resources, enabling higher utilization and better performance.

Q: What are the main BSPDN implementation approaches?

A: Three dominate: traditional backside contact, PowerVia with nanoTSVs (Intel 18A), and direct source/drain or Super Power Rail (TSMC A16). Each trades complexity against scaling.

Q: How does BSPDN change physical design?

A: Power grids no longer constrain frontside metal, so utilization rises from ~75–80% to 90%+. Cell libraries shed power rails, and IR-drop analysis spans both networks.

Q: Which foundries are adopting BSPDN and when?

A: Intel ships PowerVia at 18A first, in mid-2025. TSMC follows with A16 Super Power Rail in H2 2026, and Samsung plans BSPDN for 2GAP in 2027.

Q: Which applications benefit most from BSPDN?

A: HPC, AI accelerators, flagship mobile, and datacenter infrastructure benefit most, where power integrity, density, and area efficiency justify the added manufacturing complexity.

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RESOURCES

Pre-silicon engineering

Silicon Engineering & Semiconductor Design Services | UST

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